sample_uvm_tb/Makefile

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Makefile
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2024-08-11 21:48:11 -07:00
# Make and run project
UVM_HOME=/home/mahesh/git/uvm-verilator
PROJ=uvm_tb
SV_FILES=$(shell ls *.sv)
SV_SRC=$(UVM_HOME)/src/uvm_pkg.sv tb_pkg.sv
SV_DEPS=$(SV_FILES)
CPP_SRC=sim_$(PROJ).cpp
TIMESCALE= --timescale '1ns/1ns'
UVM_DEFINES=+define+UVM_NO_DPI \
+define+UVM_REPORT_DISABLE_FILE_LINE
DISABLED_WARNINGS=-Wno-WIDTHTRUNC -Wno-WIDTHEXPAND \
-Wno-CASTCONST -Wno-CONSTRAINTIGN \
-Wno-MISINDENT -Wno-REALCVT \
-Wno-SYMRSVDWORD -Wno-CASEINCOMPLETE
ifndef TEST_NAME
TEST_NAME=test_base
endif
build: $(SV_DEPS)
verilator -I$(UVM_HOME)/src -I. \
-o $(PROJ).sim \
--binary \
-j 4 \
--error-limit 10 \
--timing $(TIMESCALE) \
+define+SVA_ON \
$(UVM_DEFINES) \
$(DISABLED_WARNINGS) \
$(SV_SRC)
run:
if [ ! -d logs/$(TEST_NAME) ]; then mkdir -p logs/$(TEST_NAME); fi
cd logs/$(TEST_NAME) && ../../obj_dir/$(PROJ).sim +UVM_TESTNAME=$(TEST_NAME) |& tee sim.log
clean:
rm -rf obj_dir