71 lines
2.1 KiB
Systemverilog
71 lines
2.1 KiB
Systemverilog
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class seq_base extends uvm_sequence;
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testbench_env tb_env;
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`uvm_object_utils(seq_base)
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function new(string name = "seq_base");
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super.new(name);
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endfunction
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function void set_handles(testbench_env env);
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tb_env = env;
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endfunction
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virtual task body();
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bit ok = uvm_config_db#(testbench_env)::get(m_sequencer, "", "tb_env", tb_env);
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endtask
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endclass
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class seq_basic extends seq_base;
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`uvm_object_utils(seq_basic)
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function new(string name = "seq_basic");
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super.new(name);
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endfunction
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virtual task body();
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super.body();
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`uvm_info("body", $sformatf("Initiating stimulus ..."), UVM_LOW)
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fork
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begin
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d_stimulus(tb_env.tb_if.d1_if, 1);
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end
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begin
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d_stimulus(tb_env.tb_if.d2_if, 2);
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end
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join
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`uvm_info("body", $sformatf("Stimulus done."), UVM_LOW)
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endtask
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task d_stimulus(virtual design_if d_if, int inst_n);
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`uvm_info("d_stimulus", $sformatf("Inst-%0d: Initiating stimulus...", inst_n), UVM_LOW);
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repeat(20) @(negedge tb_env.tb_if.clk);
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d_if.data_in = {inst_n[15:0], 16'hd1};
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`uvm_info("d_stimulus", $sformatf("Inst-%0d: Driving data_in=0x%h", inst_n, d_if.data_in), UVM_LOW);
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repeat(50) @(negedge tb_env.tb_if.clk);
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d_if.data_in = {inst_n[15:0], 16'hd2};
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`uvm_info("d_stimulus", $sformatf("Inst-%0d: Driving data_in=0x%h", inst_n, d_if.data_in), UVM_LOW);
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repeat(20) @(negedge tb_env.tb_if.clk);
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`uvm_info("d_stimulus", $sformatf("Inst-%0d: ... stimulus done", inst_n), UVM_LOW);
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endtask
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endclass
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class seq_reset extends seq_base;
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`uvm_object_utils(seq_reset)
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function new(string name = "seq_reset");
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super.new(name);
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endfunction
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virtual task body();
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super.body();
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`uvm_info("body", $sformatf("Initiating reset..."), UVM_LOW)
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tb_env.tb_if.rst_n = 0;
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repeat(10) @(posedge tb_env.tb_if.clk);
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tb_env.tb_if.rst_n = 1;
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`uvm_info("body", $sformatf("Reset done."), UVM_LOW)
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endtask
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endclass
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