24 lines
506 B
Systemverilog
24 lines
506 B
Systemverilog
// Design and Testbench interfaces
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interface design_if (
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input clk);
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logic rst_n;
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logic [31:0] data_in;
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logic [31:0] data_out;
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modport DN (output data_out, input rst_n, clk, data_in);
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modport TB (input clk, data_out, output rst_n, data_in);
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endinterface
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interface testbench_if (
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input clk,
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virtual design_if d1_if,
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virtual design_if d2_if);
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logic rst_n;
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modport DN (input rst_n, clk);
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modport TB (input clk, output rst_n);
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endinterface
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